View ISL90840_709623.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL90840
Quad Digitally Controlled Potentiometers (XDCPTM)
Data Sheet July 27, 2005 FN8086.0
Low Noise, Low Power I2C(R) Bus, 256 Taps
The ISL90840 integrates four digitally controlled potentiometers (XDCP) on a monolithic CMOS integrated circuit. The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the I2C bus interface. Each potentiometer has an associated Wiper Register (WR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing.
Features
* Four potentiometers in one package * 256 resistor taps - 0.4% resolution * I2C serial interface - Three address pins, up to eight devices/bus * Wiper resistance: 70 typical @ 3.3V * Standby current <5A max * Power supply: 2.7V to 5.5V * 50k, 10k total resistance * 20 Lead TSSOP * Pb-free plus anneal available (RoHS compliant)
Pinout
ISL90840 (20 LEAD TSSOP) TOP VIEW
RH3 RL3 RW3 A2 SCL 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RW0 RL0 RH0 D.N.C. VCC A1 A0 RH1 RL1 RW1
Ordering Information
PART NUMBER ISL90840UIV2027 ISL90840UIV2027Z (Notes 1 & 2) ISL90840WIV2027 ISL90840WIV2027Z (Notes 1 & 2) NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Contact factory for availability. PACKAGE 20 Ld TSSOP 20 Ld TSSOP (Pb-Free) 20 Ld TSSOP 20 Ld TSSOP (Pb-Free) TEMP RANGE (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 RESISTANCE OPTION () 50K 50K 10K 10K
SDA GND RW2 RL2 RH2
Functional Diagram
VCC RH0 RH1 RH2 RH3
SCL SDA A0 A1 A2 I2C INTERFACE
GND
RL0
RW0
RL1
RW1
RL2
RW2
RL3
RW3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL90840 Block Diagram
VCC
WR3
DCP3
RH3 RW3 RL3 RH2 RW2 RL2 RH1 RW1 RL1 RH0 RW0 RL0
SDA SCL A2 A1 A0
I2C INTERFACE
POWER-UP, INTERFACE, CONTROL AND STATUS LOGIC
WR2
DCP2
WR1
DCP1
WR0
DCP0
GND
Pin Descriptions
TSSOP PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL RH3 RL3 RW3 A2 SCL SDA GND RW2 RL2 RH2 RW1 RL1 RH1 A0 A1 VCC D.N.C. RH0 RL0 RW0 "High" terminal of DCP3 "Low" terminal of DCP3 "Wiper" terminal of DCP3 Device address for the I2C interface I2C interface clock Serial data I/O for the I2C interface Device ground pin "Wiper" terminal of DCP2 "Low" terminal of DCP2 "High" terminal of DCP2 "Wiper" terminal of DCP1 "Low" terminal of DCP1 "High" terminal of DCP1 Device address for the I2C interface Device address for the I2C interface Power supply pin Do not connect "High" terminal of DCP0 "Low" terminal of DCP0 "Wiper" terminal of DCP0 DESCRIPTION
2
FN8086.0 July 27, 2005
ISL90840
Absolute Maximum Ratings
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage at any digital interface pin with respect to GND . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP pin with respect to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC Lead temperature (soldering, 10s). . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . Class II, Level B at +85C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Human Body Model
Recommended Operating Conditions
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power rating of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW Wiper current of each DCP . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0mA
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option MIN TYP (NOTE 1) 10 50 -20 VCC = 3.3V @ 25C, wiper current = VCC/RTOTAL 70 10/10/25 Voltage at pin from GND to VCC 0.1 1 +20 200 MAX UNIT k k % pF A
PARAMETER RH to RL resistance
RH to RL resistance tolerance RW CH/CL/CW ILkgDCP Wiper resistance Potentiometer capacitance (Note 15) Leakage on DCP pins (Note 15)
VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2, or 3) INL (Note 6) DNL (Note 5) ZSerror (Note 3) FSerror (Note 4) VMATCH (Note 7) TCV (Note 8) Integral non-linearity Differential non-linearity Zero-scale error Monotonic over all tap positions W option U option Full-scale error W option U option DCP to DCP matching Any two DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals DCP register set to 80 hex -1 -0.5 0 0 -7 -2 -2 1 0.5 -1 -1 1 0.5 7 2 0 0 2 LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2) ppm/C
Ratiometric temperature coefficient
4
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected. i = 0, 1, 2 or 3) RINL (Note 12) RDNL (Note 11) Roffset (Note 10) Integral non-linearity Differential non-linearity Offset W option U option RMATCH (Note 13) TCR (Note 14) DCP to DCP matching Resistance temperature coefficient Any two DCPs at the same tap position with the same terminal voltages DCP register set between 20 hex and FF hex DCP register set between 20 hex and FF hex; monotonic over all tap positions -1 -0.5 0 0 -2 45 1 0.5 1 0.5 7 2 2 MI (Note 9) MI (Note 9) MI (Note 9) MI (Note 9) MI (Note 9) ppm/C
3
FN8086.0 July 27, 2005
ISL90840
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 ISB PARAMETER VCC supply current (volatile write/read) VCC current (standby) TEST CONDITIONS fSCL = 400kHz; SDA = Open; (for I2C, active, read and write states) VCC = +5.5V, I2C interface in standby state VCC = +3.6V, I2C interface in standby state ILkgDig tDCP (Note 15) Leakage current, at pins A0, A1, A2, SDA, and SCL DCP wiper response time Voltage at pin from GND to VCC SCL falling edge of last bit of DCP data byte to wiper change -10 MIN TYP (NOTE 1) MAX 1 5 2 10 1 UNIT mA A A A s
SERIAL INTERFACE SPECS VIL VIH Hysteresis (Note 15) VOL (Note 15) Cpin (Note 15) fSCL tIN (Note 15) tAA (Note 15) tBUF (Note 15) tLOW tHIGH tSU:STA tHD:STA tSU:DAT A2, A1, A0, SDA, and SCL input buffer LOW voltage A2, A1, A0, SDA, and SCL input buffer HIGH voltage SDA and SCL input buffer hysteresis SDA output buffer LOW voltage, sinking 4mA A2, A1, A0, SDA, and SCL pin capacitance SCL frequency Pulse width suppression time at SDA and SCL inputs SCL falling edge to SDA output data valid Time the bus must be free before the start of a new transmission Clock LOW time Clock HIGH time START condition setup time START condition hold time Input data setup time Any pulse narrower than the max spec is suppressed SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition Measured at the 30% of VCC crossing Measured at the 70% of VCC crossing SCL rising edge to SDA falling edge; both crossing 70% of VCC From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC From SDA exiting the 30% to 70% of VCC window, to SCL rising edge crossing 30% of VCC From SCL rising edge crossing 70% of VCC to SDA entering the 30% to 70% of VCC window From SCL rising edge crossing 70% of VCC, to SDA rising edge crossing 30% of VCC From SDA rising edge to SCL falling edge; both crossing 70% of VCC From SCL falling edge crossing 30% of VCC, until SDA enters the 30% to 70% of VCC window From 30% to 70% of VCC 1300 -0.3 0.7*VCC 0.05* VCC 0 0.4 10 400 50 900 0.3*VCC VCC+0.3 V V V V pF kHz ns ns ns
1300 600 600 600 100
ns ns ns ns ns
tHD:DAT
Input data hold time
0
ns
tSU:STO tHD:STO tDH (Note 15) tR (Note 15)
STOP condition setup time STOP condition hod time for read, or volatile only write Output data hold time
600 600 0
ns ns ns
SDA and SCL rise time
20 + 0.1 * Cb
250
ns
4
FN8086.0 July 27, 2005
ISL90840
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL tF (Note 15) Cb (Note 15) Rpu (Note 15) tSU:A tHD:A PARAMETER SDA and SCL fall time Capacitive loading of SDA or SCL TEST CONDITIONS From 70% to 30% of VCC Total on-chip and off-chip MIN 20 + 0.1 * Cb 10 1 TYP (NOTE 1) MAX 250 400 UNIT ns pF k
SDA and SCL bus pull-up resistor off- Maximum is determined by tR and tF chip For Cb = 400pF, max is about 2~2.5k. For Cb = 40pF, max is about 15~20k A2, A1 and A0 setup time A2, A1 and A0 hold time Before START condition After STOP condition
600 600
ns ns
SDA vs SCL Timing
tF tHIGH tLOW tR
SCL tSU:STA SDA (INPUT TIMING)
tSU:DAT tHD:DAT tSU:STO
tHD:STA
tAA SDA (OUTPUT TIMING)
tDH
tBUF
A0, A1, and A2 Pin Timing
START SCL CLK 1 STOP
SDA IN tSU:A A0, A1, OR A2 tHD:A
5
FN8086.0 July 27, 2005
ISL90840
NOTES: 1. Typical values are for TA = 25C and 3.3V supply voltage. 2. LSB: [V(RW)255 - V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = V(RW)0/LSB. 4. FS error = [V(RW)255 - VCC]/LSB. 5. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting. 6. INL = V(RW)i - i - LSB - V(RW) for i = 1 to 255. 7. VMATCH = [V(RWx)i - V(RWy)i]/LSB, for i = 0 to 255, x = 0 to 3 and y = 0 to 3. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 8. TC V = --------------------------------------------------------------------------------------------- x ---------------- for i = 16 to 240 decimal, T = -40C to 85C. Max( ) is the maximum value of the wiper [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 125C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 9. MI = |R255 - R0|/255. R255 and R0 are the measured resistances for the DCP register set to FF hex and 00 hex respectively. 10. Roffset = R0/MI, when measuring between RW and RL. Roffset = R255/MI, when measuring between RW and RH. 11. RDNL = (Ri - Ri-1)/MI, for i = 32 to 255. 12. RINL = [Ri - (MI * i) - R0]/MI, for i = 32 to 255. 13. RMATCH = (Ri,x - Ri,y)/MI, for i = 0 to 255, x = 0 to 3 and y = 0 to 3. [ Max ( Ri ) - Min ( Ri ) ] 10 14. TC R = --------------------------------------------------------------- x ---------------- for i = 32 to 255, T = -40C to 85C. Max( ) is the maximum value of the resistance and Min ( ) is the [ Max ( Ri ) + Min ( Ri ) ] 2 125C minimum value of the resistance over the temperature range. 15. This parameter is not 100% tested.
6
Typical Performance Curves
160 140 WIPER RESISTANCE () 120 100 80 60 40 20 0 0 VCC=5.5, T=-40C 50 100 VCC= 5.5, T=+85C VCC=5.5, T=+25C 150 200 250 VCC=2.7, T=-40C VCC=2.7, T=+85C VCC=2.7, T=+25C STANDBY ICC (A) 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 2.7 3.2 +25C 3.7 4.2 VCC (V) 4.7 5.2 +85C -40C
TAP POSITION (DECIMAL)
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [I(RW) = VCC / RTOTAL] FOR 50k (U)
FIGURE 2. STANDBY ICC vs VCC
6
FN8086.0 July 27, 2005
ISL90840 Typical Performance Curves
0.2 0.15 0.1 DNL (LSB) INL (LSB) 0.05 0 -0.05 -0.1 -0.15 -0.2 0 VCC=5.5, T=+25C VCC=2.7, T=+85C 50 100 VCC=5.5, T=+85C 150 200 250 0.1 0 VCC=2.7, T=+25C -0.1 -0.2 0.3 VCC=2.7, T=+85C VCC=5.5, T=-40C VCC=2.7, T=+25C
(Continued)
0.3
VCC=2.7, T=-40C 0.2
VCC=2.7, T=-40C VCC=5.5, T=-40C VCC=5.5, T=+85C
0
50
100
150
200
250
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
0.4
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
0
0.35 ZSerror (LSB) FSerror (LSB)
-0.2 VCC=5.5V -0.4
0.3 2.7V 0.25
-0.6
VCC=2.7V
0.2
5.5V
-0.8
0.15 -40
-20
0
20
40
60
80
-1 -40
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. ZSerror vs TEMPERATURE FOR 50k (W)
0.3 VCC=2.7, T=+25C 0.2 0.1 VCC=5.5, T=+25C
FIGURE 6. FSerror vs TEMPERATURE FOR 50k (W)
0.5 VCC=2.7, T=+25C 0.3 VCC=5.5, T=-40C VCC=5.5, T=+85C VCC=2.7, T=+85C -0.1
DNL (LSB)
0 -0.1 VCC=5.5, T=+85C -0.2 -0.3 32 VCC=2.7, T=-40C 82 132 VCC=2.7, T=+85C
INL (LSB)
0.1
-0.3 VCC=5.5, T=+25C 82 132 182 VCC=2.7, T=-40C 232
VCC=5.5, T=-40C 182 232
-0.5 32
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 50k (U)
7
FN8086.0 July 27, 2005
ISL90840 Typical Performance Curves
1.5 END TO END RTOTAL CHANGE (%) 1 0.5 0 -0.5 -1 -1.5 -40 -20 32 2.7V 5.5V TC (ppm/C) 10
(Continued)
20
0
-10
-20
0
20
40
60
80
82
132
182
232
TEMPERATURE (C)
TAP POSITION (DECIMAL)
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE FOR 50k (W)
35 25 15 5 -5 -15 -25 32
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FOR 50k (W)
INPUT
TC (ppm/C)
OUTPUT
82
132
182
232
TAP POSITION = MID POINT RTOTAL=9.4K
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FOR 50k (W)
FIGURE 12. FREQUENCY RESPONSE (2.2MHz)
SIGNAL AT WIPER (WIPER UNLOADED)
SCL
SIGNAL AT WIPER (WIPER UPLOADED MOVEMENT FROM ffh TO 00h WIPER MOVEMENT MID POINT FROM 80h TO 7fh
FIGURE 13. MIDSCALE GLITCH, CODE 80h TO 7Fh (WIPER 0)
FIGURE 14. LARGE SIGNAL SETTLING TIME
8
FN8086.0 July 27, 2005
ISL90840 Principles of Operation
The ISL90840 is an integrated circuit incorporating four DCPs with their associated registers, and an I2C serial interface providing direct communication between a host and the potentiometers. All I2C interface operations must begin with a START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The ISL90840 continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition is met (See Figure 15). A START condition is ignored during the powerup of the device. All I2C interface operations must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH (See Figure 15). A STOP condition at the end of a read operation, or at the end of a write operation places the device in its standby mode. An ACK, Acknowledge, is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 16). The ISL90840 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and once again after successful receipt of an Address Byte. The ISL90840 also responds with an ACK after receiving a Data Byte of a write operation. The master must respond with an ACK after receiving a Data Byte of a read operation A valid Identification Byte contains 0101 as the four MSBs, and the following three bits matching the logic values present at pins A2, A1, and A0. The LSB is the Read/Write bit. Its value is "1" for a Read operation, and "0" for a Write operation (See Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT
Logic values at pins A2, A1, and A0 respectively
DCP Description
Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 8-bit volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR<7:0>: 00h), its wiper terminal (RW) is closest to its "Low" terminal (RL). When the WR of a DCP contains all ones (WR<7:0>: FFh), its wiper terminal (RW) is closest to its "High" terminal (RH). As the value of the WR increases from all zeroes (00h) to all ones (255 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL90840 is being powered up, all four WRs are reset to 80h (128 decimal), which locates RW roughly at the center between RL and RH. The WRs can be read or written to directly using the I2C serial interface as described in the following sections. The I2C interface Address Byte has to be set to 00h, 01h, 02h, and 03h to access the WR of DCP0, DCP1, DCP2, and DCP3 respectively
I2C Serial Interface
The ISL90840 supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. The device controlling the transfer is a master and the device being controlled is the slave. The master always initiates data transfers and provides the clock for both transmit and receive operations. Therefore, the ISL90840 operates as a slave device in all applications. All communication over the I2C interface is conducted by sending the MSB of each byte of data first.
0 (MSB)
1
0
1
A2
A1
A0
R/W (LSB)
Protocol Conventions
Data states on the SDA line must change only during SCL LOW periods. SDA state changes during SCL HIGH are reserved for indicating START and STOP conditions (See Figure 15). On power-up of the ISL90840 the SDA pin is in the input mode.
9
FN8086.0 July 27, 2005
ISL90840
SCL
SDA
START
DATA STABLE
DATA CHANGE
DATA STABLE
STOP
FIGURE 15. VALID DATA CHANGES, START, AND STOP CONDITIONS
SCL FROM MASTER
1
8
9
SDA OUTPUT FROM TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM RECEIVER START
HIGH IMPEDANCE
ACK
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
WRITE SIGNALS FROM THE MASTER S T A R T S T O P
IDENTIFICATION BYTE
ADDRESS BYTE
DATA BYTE
SIGNAL AT SDA SIGNALS FROM THE ISL90840
0 1 0 1 A2 A1 A0 0 A C K
000000 A C K A C K
FIGURE 17. BYTE WRITE SEQUENCE
SIGNALS FROM THE MASTER
S T A R T
IDENTIFICATION BYTE WITH R/W=0
ADDRESS BYTE
S T A IDENTIFICATION R BYTE WITH T R/W=1
A C K
A C K
S T O P
SIGNAL AT SDA
0 1 0 1 A2 A1 A0 0 A C K
000000 A C K
0 1 0 1 A2 A1 A0 1 A C K
SIGNALS FROM THE SLAVE
FIRST READ DATA BYTE
LAST READ DATA BYTE
FIGURE 18. READ SEQUENCE
10
FN8086.0 July 27, 2005
ISL90840 Write Operation
A Write operation requires a START condition, followed by a valid Identification Byte, a valid Address Byte, a Data Byte, and a STOP condition. After each of the three bytes, the ISL90840 responds with an ACK. At this time, the device enters its standby state (See Figure 17).
Read Operation
A Read operation consist of a three byte instruction followed by one or more Data Bytes (See Figure 18). The master initiates the operation issuing the following sequence: a START, the Identification byte with the R/W bit set to "0", an Address Byte, a second START, and a second Identification byte with the R/W bit set to "1". After each of the three bytes, the ISL90840 responds with an ACK. Then the ISL90840 transmits Data Bytes as long as the master responds with an ACK during the SCL cycle following the eighth bit of each byte. The master terminates the read operation (issuing a STOP condition) following the last bit of the last Data Byte (See Figure 18). The Data Bytes are from the registers indicated by an internal pointer. This pointer initial value is determined by the Address Byte in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 03h, the pointer "rolls over" to 00h, and the device continues to output data for each ACK received.
11
FN8086.0 July 27, 2005
ISL90840 Packaging Information
20-Lead Plastic, TSSOP, Package Code V20
.025 (.65) BSC
.169 (4.3) .252 (6.4) BSC .177 (4.5)
.252 (6.4) .260 (6.6)
.041 (1.05) .0075 (.19) .0118 (.30) .002 (.05) .006 (.15)
.010 (.25) Gage Plane 0 - 8 .019 (.50) .029 (.75) Detail A (20X) Seating Plane
.031 (.80) .041 (1.05) See Detail "A"
NOTE: All dimensions in inches (in parentheses in millimeters).
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN8086.0 July 27, 2005

▲Up To Search▲

Price & Availability of ISL90840

	To Download ISL90840 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .